14,819 research outputs found

    Multidimensional Localized Solitons

    Full text link
    Recently it has been discovered that some nonlinear evolution equations in 2+1 dimensions, which are integrable by the use of the Spectral Transform, admit localized (in the space) soliton solutions. This article briefly reviews some of the main results obtained in the last five years thanks to the renewed interest in soliton theory due to this discovery. The theoretical tools needed to understand the unexpected richness of behaviour of multidimensional localized solitons during their mutual scattering are furnished. Analogies and especially discrepancies with the unidimensional case are stressed

    Economies of Scale for Real Estate Investment Trusts

    Get PDF
    Using the translog cost function to estimate economies of scale for a sample of Real Estate Investment Trusts for the years 1992-1994, we find significant evidence that economies of scale exist for REITs for all years examined. The results show that measurement of scale economies is sensitive to the model used for the measurement. Individual characteristics of the REIT, such as type of management and degree of leverage, affect the magnitude of the scale economy. Additional variables accounting for property type diversification and geographic influences have little additional impact on the measured scale economies. Finally, the measured economies of scale for REITs vary considerably over time.

    Waves in the Skyrme--Faddeev model and integrable reductions

    Full text link
    In the present article we show that the Skyrme--Faddeev model possesses nonlinear wave solutions, which can be expressed in terms of elliptic functions. The Whitham averaging method has been exploited in order to describe slow deformation of periodic wave states, leading to a quasi-linear system. The reduction to general hydrodynamic systems have been considered and it is compared with other integrable reductions of the system.Comment: 16 pages, 5 figure

    Impact of Correlated Mobility on Delay-Throughput Performance in Mobile Ad-Hoc Networks

    Get PDF
    Abstract—We extend the analysis of the scaling laws of wireless ad hoc networks to the case of correlated nodes movements, which are commonly found in real mobility processes. We consider a simple version of the Reference Point Group Mobility model, in which nodes belonging to the same group are constrained to lie in a disc area, whose center moves uniformly across the network according to the i.i.d. model. We assume fast mobility conditions, and take as primary goal the maximization of pernode throughput. We discover that correlated node movements have huge impact on asymptotic throughput and delay, and can sometimes lead to better performance than the one achievable under independent nodes movements. I. INTRODUCTION AND RELATED WORK In the last few years the store-carry-forward communication paradigm, which allows nodes to physically carry buffered dat

    Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding

    Get PDF
    Real-time and high-quality video coding is gaining a wide interest in the research and industrial community for different applications. H.264/AVC, a recent standard for high performance video coding, can be successfully exploited in several scenarios including digital video broadcasting, high-definition TV and DVD-based systems, which require to sustain up to tens of Mbits/s. To that purpose this paper proposes optimized architectures for H.264/AVC most critical tasks, Motion estimation and context adaptive binary arithmetic coding. Post synthesis results on sub-micron CMOS standard-cells technologies show that the proposed architectures can actually process in real-time 720 × 480 video sequences at 30 frames/s and grant more than 50 Mbits/s. The achieved circuit complexity and power consumption budgets are suitable for their integration in complex VLSI multimedia systems based either on AHB bus centric on-chip communication system or on novel Network-on-Chip (NoC) infrastructures for MPSoC (Multi-Processor System on Chip
    corecore